ucsdsysnet / corundum, Hacker News

GitHub repository:https://github.com/ucsdsysnet/corundum

********** Introduction

Corundum is an open-source, high-performance FPGA-based NIC. Features include a high performance datapath, (G /) *********************************************************************************************** (G /) ************************************************************************ G Ethernet, PCI express gen 3, a custom, high performance, tightly-integrated PCIe DMA engine, many (01575879 ) transmit, receive, completion, and event queues, MSI interrupts, multiple interfaces, multiple ports per interface, per-port transmit scheduling including high precision TDMA, flow hashing, RSS, checksum offloading, and native IEEE PTP timestamping. A Linux driver is included that integrates with the Linux networking stack. Development and debugging is facilitated by an extensive simulation framework that covers the entire system from a simulation model of the driver and PCI express interface on one side to the Ethernet interfaces on the other side.

Corundum has several unique architectural features. First, transmit, receive, completion, and event queue states are stored efficiently in block RAM or ultra RAM, enabling support for thousands of individually-controllable queues. These queues are associated with interfaces, and each interface can have multiple ports, each with its own independent scheduler. This enables extremely fine-grained control over packet transmission. Coupled with PTP time synchronization, this enables high precision TDMA.

Corundum currently supports Xilinx Ultrascale and Ultrascale Plus series devices. Designs are included for the following FPGA boards:

Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale Plus XCVU3P)

Exablaze ExaNIC X (Xilinx Kintex Ultrascale XCKU) )

Exablaze ExaNIC X (Xilinx Kintex Ultrascale Plus XCKU3P)

Xilinx VCU (Xilinx Virtex Ultrascale XCVU 108

Xilinx VCU (Xilinx Virtex Ultrascale Plus) XCVU9P)

For operation at G and G, Corundum uses the open source (G /) *************************************************************************************** G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are required. However, it is possible to use other MAC and / or PHY modules. Operation at G currently requires using the Xilinx CMAC core with RS-FEC enabled, which is covered by the free CMAC license on Xilinx Ultrascale parts.

Documentation (Modules)

Frame pad module for (bit) *************************** G CMAC TX interface. Zero pads transmit frames to minimum bytes.

Completion operation multiplexer module. Merges completion write operations from different sources to enable sharing a single cpl_write module instance.

Completion queue manager module. Stores device to host queue state in block RAM or ultra RAM.

Completion write module. Responsible for writing completion and event entries into host memory.

desc_fetch module
desc_op_mux module

Descriptor operation multiplexer module. Merges descriptor fetch operations from different sources to enable sharing a single cpl_write module instance.

Event mux module. Enables multiple event sources to feed the same event queue.

interface module

Interface module. Contains the event queues, interface queues, and ports.

Port module. Contains the transmit and receive engines

queue_manager module

Queue manager module. Stores host to device queue state in block RAM or ultra RAM.

Receive checksum computation module. Computes bit checksum of Ethernet frame payload to aid in IP checksum offloading.

rx_engine module

Receive engine. Manages receive descriptor dequeue and fetch via DMA, packet reception, data writeback via DMA, and completion enqueue and writeback via DMA. Handles PTP timestamps for inclusion in completion records.

Receive hash computation module. Extracts IP addresses and ports from packet headers and computes bit Toeplitz flow hash.

tdma_ber_ch module

TDMA bit error ratio test channel module. Controls PRBS logic in Ethernet PHY and accumulates bit errors. Can be configured to bin error counts by TDMA timeslot.

************************************

TDMA bit error ratio test test module. Wrapper for a tdma_scheduler and multiple instances of tdma_ber_ch.

************************************tdma_scheduler module

TDMA scheduler module. Generates TDMA timeslot index and timing signals from PTP time.

**************************************tx_checksum module

tx_engine module

Transmit engine. Manages receive descriptor dequeue and fetch via DMA, packet data fetch via DMA, packet transmission, and completion enqueue and writeback via DMA. Handles PTP timestamps for inclusion in completion records.

****************************************tx_scheduler_ctrl_tdma module

tx_scheduler_rr module

Round-robin transmit scheduler. Determines which queues from which to send packets.

Source Files (*********************************** cmac_pad.v : Pad frames to bytes for CMAC TX cpl_op_mux.v: Completion operation mux cpl_queue_manager.v: Completion queue manager cpl_write.v: Completion write module desc_fetch.v: Descriptor fetch module desc_op_mux.v: Descriptor operation mux event_mux.v: Event mux event_queue.v: Event queue interface.v: Interface port.v: Port queue_manager.v: Queue manager rx_checksum.v: Receive checksum offload rx_engine.v: Receive engine rx_hash.v: Receive hashing module tdma_ber_ch.v: TDMA BER channel tdma_ber.v: TDMA BER tdma_scheduler.v: TDMA scheduler tx_checksum.v: Transmit checksum offload tx_engine.v: Transmit engine tx_scheduler_ctrl_tdma.v: TDMA transmit scheduler controller tx_scheduler_rr.v: Round robin transmit scheduler

Running the included testbenches requires MyHDL and Icarus Verilog. Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.

Corundum internally uses the following libraries:
**************************************************** https://github.com/alexforencich/ verilog-axi
https://github.com/alexforencich/verilog-axis
https://github.com/alexforencich/verilog-ethernet
https://github.com/alexforencich/verilog-pcie
https://github.com/solemnwarning/timespec
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