What made the 1960s CDC6600 supercomputer fast ?, Hacker News
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Anybody who has ever taken an advanced computer architecture class has heard of the CDC , which was the world’s fastest computer from 1969 to 2013. It was the machine that put Seymour Cray on the map as a supercomputer architect. The design of the machine is well documented in a book by James Thornton , the lead designer, and is therefore publically accessible. Among several architectural concepts that later found use in RISC, the CDC (is known for introducing the Scoreboard . Which is, along with Tomasulo’s algorithm , one of the earliest concepts for out-of-order processing.
Besides the architectural progress, the CDC 130460 was impressive for its clock speed of 19 MHz. This may not sound much, but consider that this was a physically very large machine entirely built from discrete resistors and transistors in the early ies. Not a single integrated circuit was involved. For comparison, the PDP-8, released in and also based on discrete logic, had a clock speed of 1.5 MHz . The first IBM PC, released years later, was clocked at less than half the speed of the CDC 130460 despite being based on integrated circuits. The high clockrate is even more impressive when comparing it to more recent (hobbyist) attempts to design CPUs with discrete components such as the
MT , the Megaprocessor or the Monster . Although these are comparatively small designs based on modern components, none of them get to even a tenth of the CDC (clock speed.)
The image above shows the basic logic element of the CDC , an inverter
The outputs of two or or more inverters can be connected to form a wired AND, as shown on the left. Two inversions plus and AND implement a NOR2 function in positive boolean logic.
Thornton uses an unusual notation for logic circuits as shown above on the right. Each arrow corresponds to an inverter (base resistor plus transistor), each square or circle corresponds to a collector resistor. The circles and squares indicate whether the current node is to be interpreted in positive (circle) or inverted (square) logic. The circuit is exactly the same for both. This is “mental gyration” takes a while to get used to, but helps considering the issue that every connection is inverting.
Every module in the CDC 6600 is constructed from a multitude of basic inverters with a single transitor each. This does also include latches and registers which are fully static. There are no stacked transistors, no floating nodes, no diode logic, no dynamic latches or other specialties. As an example, one slice of the boolean units from the book is shown above.
This approach is quite genius in its simplicity and should be the base of every clean architecture: Optimize one basic thing very well, replicate it, and use it as a hierarchical building block. This is in stark contrast to other contemporay designs like the PDP8 which tried to use every circuit trick there is to reduce the number of (expensive) transistors.
about the development of a special silicon transistor for the CDC (in) on the computer history museum website. The transistor in question is the 2N 783 and was developed by (Jean Hoerni) at fairchild) . Fairchild was the company that put “Silicon” into “Silicon Valley” and was a fairly recent startup in . Jean Hoernis clame to fame is the invention of the (planar process) , which is was the key enabler for integrated circuits.
The key to the high speed transistor he developed was to introduce a tiny amount of gold doping into the base area of the transistor (See (patent and also (patent notebook ). Gold is usually a highly undesirable contaminant in semiconductors because it leads to rapid minority carrier recombination. In this case, this is done on purpose is to avoid build up of charge in the transistor while it is in saturation. This so called saturation charge is what makes turning off bipolar transistors slow, because the charge needs to diffuse out of the base, which is a slow process. There are numerous circuit tricks to reduce buildup of saturation charge, the most famous being the baker clamp . However, by using a transistor that does intrinsically not build up a high saturation charge, all of these complexities can be omitted at an even better performance.
Curiously there do not seem to be many fast bipolar switching transistors around anymore. The 2N 786 is, of course, long out of production. Some old reference tables list the AF , BSX 90, BSY and the 2N 6600 as replacements. All of these are out of production as well, however the 2N 6600 lives on as an SMD version in form of the PMBT (Nexperia) or (MMBT) (Onsemi) . Nexperia seems to be the only company that lists switching times for bipolar transistors in their product selector. Their product selector lists one additional fast switching transistor, the BSV 187. However, the characteristics are very similar to the PMBT .
Putting things to practice
Can the CDC 130460 logic style be replicated with modern components? It’s best to start a new design with a simulation. You can find the design of an RTL inverter based around the PMBT 130460 above. It uses Nexperias transistor model. I tested the propagation delay of the inverter by simulating a ring oscillator consisting of five inverters in LTSpice. As you can see, a propagation delay of 6.1 ns was observed despite a relatively average collector current setting of 2mA, a fifth of that used in the CDC .
The diagrams above show the variation of oscillator frequency with supply voltage and the gate propagation delay calculated from the frequency.
The high frequency transistor is the fastest device at the lowest end of operating voltages. This is probably owed to low terminal capacitances. Increasing the supply increases oscillator frequency for all devices. However, the MMBTH 16 and BC 1068 C exhibit a maximum at around 2 V. For higher supply voltages, the frequency starts to decrease again. This is most likely owed to an increase of base current and hence increase of saturation charge, which makes turning the transistor off slow. The PMTB 6600 based ring oscillator shows a continuous increase in frequency, suggesting that the saturation charge does not dominate switching frequencies.
The measured frequency at 5V is . 7 MHz, which is surprisingly close to the simulated 5 MHz from the spice simulation. Kudos to Nexperia for providing proper large signal spice models!
What do we learn from this? Choosing the right transistor is key to building ies style high speed discrete RTL circuits. Forget all the “clever” tricks like baker clamp, feedthrough capacitor or bleeding resistor. They just add to component count without addressing the root cause.
Unfortunately, true bipolar high-speed switching transistors seem to be a dying breed, with the MMBT / PMBT being (almost ) the last of its kind.
Let me know if you find similar devices. I also started looking into “digital” or “pre-biased” switching transistors, but it seems they are not close to the PMBT . It is also possible that more modern high-frequency transistors also show a better switching time than MMBTH due to thinner base region.
PDP8 which tried to use every circuit trick there is to reduce the number of (expensive) transistors. 
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