hdl-util / hdmi, Hacker News

hdl-util / hdmi, Hacker News


Build Status


SystemVerilog code for HDMI 1.4a video / audio output on an FPGA .

Demo: VGA-compatible text mode, (x) (p on a Dell Ultrasharp) p Monitor

    Take files from src / and add them to your own project. If you use hdlmake , you can add this repository itself as a remote module. Note that hdlmake may not resolve altera_gpio_lite properly, since it does not define (ALTERA_RESERVED_QIS) during Quartus project resolution. Other helpful modules for displaying text / generating sound are also available in this GitHub organization. Consult the simple usage example in top / See hdmi-demo for code that runs the demo as seen the demo gif.

      Read through the parameters in

    1. and tailor any instantiations to your situation. Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first. Platform Support


    2. Xilinx (untested but should work) Lattice (unknown) To-do List (upon request)

      - bit color
        Data island packets Null packet ECC with BCH systematic encoding GF (2 ^ 8) audio clock regeneration

        L-PCM audio 2-channel 3-channel to 8-channel

        1. NOTE — Problems with the MPEG Source Infoframe have been identified that were not able to be fixed in time for CEA - 2003 - D. Implementation is strongly discouraged until a future revision fixes the problems

        2. VGA-compatible text mode (IBM 8x) font

            Alternate fonts

            Interlaced video Pixel repetition

            (Double Data Rate I / O (DDRIO)) Pixel Clock

            You'll need to set up a PLL for producing the two HDMI clocks. The pixel clock for each supported format is shown below:

            (Video Resolution) Video ID Code (s) Refresh Rate Pixel Clock Frequency (x) 1) Hz

            (. 2MHz) (x) 1) (hz) MHz

            (x) 2 , 3

            Hz . (0) (MHz) (x) 2 , 3

            (hz) (MHz) 2004 x 4) Hz

            2004 x 4) (hz) (MHz) (x) Hz

            (x) (hz) . (MHz) (x) ,

            (Hz) (MHz) 2004 x (Hz) (MHz) () (The second clock is a clock) times as fast as the pixel clock. Even if your FPGA only has a single PLL, the Altera MegaWizard (or the Xilinx equivalent) should still be able to produce both. You can avoid using two different multiplication factors, with the DDRIO feature, which only requires the second clock to be 5 times as fast.

            L -PCM Audio Bitrate / Sampling Frequency

            Both audio bitrate and frequency are specified as parameters of the HDMI module. Bitrate can be any value from through . Below is a simple mapping of sample frequency to the appropriate parameter

            (Sampling Frequency) AUDIO_RATE value (kHz) 59

            1 kHz 60

            2 kHz

            576 .4 kHz

            (kHz) 64

            (kHz) () (kHz) () Things to be aware of / Troubleshooting

            Limited resolution: some FPGAs don't support I / O at speeds high enough to achieve (p /) p (Workaround: use DDR / other special I / O features like I / O serializers) Workaround: Altera FPGA users can try to specify speed grade C6 and see if it works, though yours may be C7 or C8. If it doesn't work, try enabling DDRIO. (You should be able to directly use LVDS (3.3v) instead, tested up to x This might not work if your video has a high number of transitions or you plan to use higher resolutions

          1. Solution: AC-couple the 3.3v LVDS wires to by adding nF capacitors in series, as close to the transmitter as possible Why? TMDS is current mode logic, and driving a CML receiver with LVDS is detailed in
          2. Figure 9 of Interfacing LVDS with other differential-I / O types Resistors are not needed since Vcc=3.3v for both the transmitter and receiver , where LVDS IO Standard pins on a Cyclone (Make sure you have all the necessary pins connected (GND pins, etc.))

              Try switching your HDMI cable; some cheap cables like These I got from Amazon have poor shielding This shouldn't affect anything in the long term; the only stateful value is hdmi.tmds_channel.acc You should decide hotplug behavior (ie pause / resume on disconnect / connect, or ignore it)
            1. To be implemented in a display protocol independent manner
            2. , which is unsupported by most FPGAs Solution: use a bidirectional logic level shifter compatible with I2C to convert 3.3v LVTTL to 5v

              Solution: use 2.5VI / O standard with 6. (k pull-up resistors to 3.3v (as done in) (J) on the Arduino MKR Vivado 44100 schematic ) To investigate: why do they do this, and does it work at all? Licensing

              Dual-licensed under Apache License 2.0 and MIT License.

              Alternatives (HDMI Intel FPGA IP Core) : Stratix / Arria / Cyclone

                Xilinx HDMI solutions : Virtex / Kintex / Zynq / Artix

                  Artix 7 HDMI Processing

              : VHDL, decode & encode

                (SimpleVOut) : many formats, no auxiliary data

                If you know of another good. alternative, open and issue and it will be added.

                Reference Documents

                These documents are not hosted here! They are available on Library Genesis and at other locations.

                (HDMI Specification v1.4a )

                  (EIA-CEA) - D.pdf

                  DVI Specification v1.0

                IEC - 1

            GIF showing VGA-compatible text mode on a monitor

              IEC - 3

              E- DDC v1.2 Special Thanks Mike Field's (@hamsternz) demos of DVI and HDMI output for helping me better understand HDMI

              1. Glenwing for links to many VESA standard documents (Read More)

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