)
SystemVerilog code for HDMI 1.4a video / audio output on an FPGA .
Take files from src / and add them to your own project. If you use hdlmake , you can add this repository itself as a remote module. Note that hdlmake may not resolve altera_gpio_lite properly, since it does not define (ALTERA_RESERVED_QIS) during Quartus project resolution. Other helpful modules for displaying text / generating sound are also available in this GitHub organization. Consult the simple usage example in top / top.sv See hdmi-demo
for code that runs the demo as seen the demo gif.
Read through the parameters in
- hdmi.sv
and tailor any instantiations to your situation. Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first.
Altera
- Xilinx (untested but should work) Lattice (unknown)
- bit color
To-do List (upon request)
Platform Support
Usage
- Take files from
- hdmi.sv
and tailor any instantiations to your situation.
Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first.
Platform Support
Altera
- Xilinx (untested but should work) Lattice (unknown)
To-do List (upon request)
- bit color
- Xilinx (untested but should work) Lattice (unknown)
src / and add them to your own project. If you use hdlmake , you can add this repository itself as a remote module. Note that hdlmake may not resolve altera_gpio_lite properly, since it does not define (ALTERA_RESERVED_QIS) during Quartus project resolution. Other helpful modules for displaying text / generating sound are also available in this GitHub organization. Consult the simple usage example in top / top.sv See hdmi-demo
for code that runs the demo as seen the demo gif.
Read through the parameters in
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